? semiconductor components industries, llc, 2012 november, 2012 ? rev. 1 1 publication order number: NTNS3193NZ/d NTNS3193NZ small signal mosfet 20 v, 224 ma, single n ? channel, 0.62 x 0.62 x 0.4 mm xllga3 package features ? single n ? channel mosfet ? ultra small and thin package (0.62 x 0.62 x 0.4 mm) ? low r ds(on) solution in 0.62 x 0.62 mm package ? 1.5 v gate voltage rating ? these devices are pb ? free, halogen free/bfr free and are rohs compliant applications ? small signal load switch ? analog switch ? high speed interfacing ? optimized for power management in ultra portable products maximum ratings (t j = 25 c unless otherwise stated) parameter symbol value units drain-to-source voltage v dss 20 v gate-to-source voltage v gs 8.0 v continuous drain current (note 1) steady state t a = 25 c i d 224 ma t a = 85 c 162 t 5 s t a = 25 c 241 power dissipa- tion (note 1) steady state t a = 25 c p d 120 mw t 5 s t a = 25 c 139 pulsed drain current t p = 10 s i dm 673 ma operating junction and storage temperature t j , t stg -55 to 150 c source current (body diode) i s 120 ma lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. thermal resistance ratings parameter symbol max units junction-to-ambient ? steady state (note 1) r ja 1040 c/w junction-to-ambient ? t 5 s (note 1) r ja 900 1. surface mounted on fr4 board using the minimum recommended pad size, (or 2 mm 2 ), 1 oz cu. 2. pulse test: pulse width 300 s, duty cycle 2%. http://onsemi.com g (1) s (2) n ? channel mosfet d (3) 20 v 1.9 @ 2.5 v 1.4 @ 4.5 v r ds(on) max i d max v (br)dss mosfet xllga3 case 713ab a = specific device code m = date code 2.2 @ 1.8 v marking diagram 4.3 @ 1.5 v 224 ma device package shipping ? ordering information NTNS3193NZt5g xllga3 (pb ? free) 8000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. 1 2 3 a m 1
NTNS3193NZ http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise specified) parameter symbol test condition min typ max units off characteristics drain-to-source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 20 v drain-to-source breakdown voltage temperature coefficient v (br)dss /t j i d = ? 250 a, ref to 25 c 19 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 20 v t j = 25 c 1.0 a gate-to-source leakage current i gss v ds = 0 v, v gs = 8.0 v 2.0 a on characteristics (note 3) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 0.4 1.0 v negative gate threshold temperature coefficient v gs(th) /t j 1.9 mv/ c drain-to-source on resistance r ds(on) v gs = 4.5 v, i d = 100 ma 0.65 1.4 v gs = 2.5 v, i d = 50 ma 0.9 1.9 v gs = 1.8 v, i d = 20 ma 1.1 2.2 v gs = 1.5 v, i d = 10 ma 1.4 4.3 forward transconductance g fs v ds = 5 v, i d = 100 ma 0.56 s source ? drain diode voltage v sd v gs = 0 v, i s = 10 ma 0.55 1.0 v charges & capacitances input capacitance c iss v gs = 0 v, f = 1 mhz, v ds = 15 v 15.8 pf output capacitance c oss 3.5 reverse transfer capacitance c rss 2.4 total gate charge q g(tot) v gs = 4.5 v, v ds = 15 v, i d = 200 ma 0.70 nc threshold gate charge q g(th) 0.05 gate ? to ? source charge q gs 0.14 gate ? to ? drain charge q gd 0.10 switching characteristics, vgs = 4.5 v (note 3) turn-on delay time t d(on) v gs = 4.5 v, v dd = 15 v, i d = 200 ma, r g = 2 18 ns rise time t r 35 turn-off delay time t d(off) 201 fall time t f 110 3. switching characteristics are independent of operating junction temperatures.
NTNS3193NZ http://onsemi.com 3 typical characteristics figure 1. on ? region characteristics figure 2. transfer characteristics v ds , drain ? to ? source voltage (v) v gs , gate ? to ? source voltage (v) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.1 0.3 0.4 0.6 0.7 0.9 1.0 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.1 0.3 0.4 0.6 0.7 0.9 1.0 figure 3. on ? resistance vs. gate ? to ? source voltage figure 4. on ? resistance vs. drain current and gate voltage v gs , gate voltage (v) i d , drain current (a) 4.0 3.5 4.5 3.0 2.5 2.0 1.5 1.0 0 1.0 2.0 2.5 3.0 4.0 4.5 5.0 1.0 0.7 0.6 0.5 0.3 0.2 0.1 0 0 0.5 1.5 2.0 3.0 3.5 4.5 5.0 figure 5. on ? resistance variation with temperature figure 6. drain ? to ? source leakage current vs. voltage v ds , drain ? to ? source voltage (v) 18 16 14 12 10 6 4 2 1 10 100 1000 i d , drain current (a) i d , drain current (a) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance ( ) i dss , leakage (na) r ds(on) , normalized drain ? to ? source resistance 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.8 ? 50 ? 25 0 25 50 75 100 125 150 t j , junction temperature ( c) v gs = 4.5 v i d = 100 ma v gs = 1.8 v i d = 20 ma 0.2 0.5 0.8 v gs = 2.5 v 3.0 v 2.0 v 1.5 v 1.8 v 1.2 v 0.2 0.5 0.8 v ds = 5 v t j = 25 c t j = 125 c t j = ? 55 c 1.5 3.5 t j = 25 c i d = 0.1 a 0.4 0.8 0.9 1.0 2.5 4.0 t j = 25 c v gs = 2.5 v v gs = 1.8 v 820 t j = 85 c t j = 125 c 3.5 v 4.0 v 4.5 v v gs = 1.5 v 1.6 1.7 0.5 v gs = 4.5 v
NTNS3193NZ http://onsemi.com 4 typical characteristics t d(on) figure 7. capacitance variation figure 8. gate ? to ? source and drain ? to ? source voltage vs. total charge v ds , drain ? to ? source voltage (v) q g , total gate charge (nc) 18 16 12 10 6 4 2 0 0 5 15 20 25 30 0.7 0.6 0.3 0.2 0.1 0 0 1 2 3 4 5 figure 9. resistive switching time variation vs. gate resistance figure 10. diode forward voltage vs. current r g , gate resistance ( ) v sd , source ? to ? drain voltage (v) 100 10 1 10 100 1000 1.2 1.1 1.0 0.8 0.7 0.6 0.5 0.4 0.01 0.1 1 10 figure 11. threshold voltage figure 12. maximum rated forward biased safe operating area v ds , drain ? to ? source voltage (v) 100 10 1 0.1 0.001 0.01 0.1 1 c, capacitance (pf) v gs , gate ? to ? source voltage (v) t, time (ns) i s , source current (a) i d , drain current (a) t j , temperature ( c) v gs(th) , gate ? to ? source threshold voltage (v) 0.85 ? 50 ? 25 0 25 50 75 100 125 150 i d = 250 a 0.75 0.65 0.55 0.45 0.35 81420 10 v gs = 0 v t j = 25 c f = 1 mhz c iss c oss c rss v gs = 4.5 v v dd = 15 v t d(off) t r t f 0 3 6 12 15 18 9 0.4 0.5 0.8 v ds , drain ? to ? source voltage (v) v ds = 15 v t j = 25 c i d = 0.2 a 0.9 1.3 t j = 25 c t j = 125 c t j = ? 55 c v gs 8 v single pulse t c = 25 c r ds(on) limit thermal limit package limit dc 10 s 100 s 1 ms 10 ms q t v ds v gs q gs q gd
NTNS3193NZ http://onsemi.com 5 typical characteristics figure 13. fet thermal response t, time (s) 1e ? 02 1e ? 01 1e ? 06 0 200 400 600 800 900 1100 1200 r(t), effective transient thermal response ( c/w) 1000 700 500 300 100 1e ? 05 1e ? 04 1e ? 03 1e+00 1e+01 1e+02 1e+03 r ja steady state = 1040 c/w duty cycle = 0.5 single pulse 0.20 0.10 0.05 0.02 0.01 solder footprint* dimensions: millimeters 0.62 0.35 0.20 0.20 minimum recommended pitch 2x 2x 0.28 0.60 1 2 3 *dependent upon end user capabilities, this footprint could be used as a minimum.
NTNS3193NZ http://onsemi.com 6 package dimensions case 713ab issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. a b e d bottom view b top view 0.10 c a a1 0.10 c 0.10 c c seating plane side view dim min max millimeters a 0.340 0.440 a1 0.000 0.030 b 0.100 0.200 d 0.620 bsc e 0.620 bsc l 0.090 0.210 solder footprint* dimensions: millimeters 0.760 0.350 0.200 *additional information concerning board mounting for this package may be found in document and9099/d, ?board level application note for xllga 3-lead 0.62x0.62 package?. for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 1 l2 0.110 0.310 l l2 0.280 recommended pitch e2 0.400 0.600 d2 0.175 bsc d3 0.205 bsc e 0.350 bsc k 0.200 ref 0.10 c a m 0.10 b c m 0.05 c 2x e e/2 d3 e2 k a m 0.10 b c m 0.05 c 2x 2x 2x 0.350 0.600 1 pin one reference 3x d2 2 3 2 3 package outline on semiconductor and are registered trademar ks of semiconductor components industries, llc (s cillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to an y products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of th e application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products ar e not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associ ated with such unintended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action em ployer. this literature is subject to all applicable copyrig ht laws and is not fo r resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NTNS3193NZ/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
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